1. Field of the Invention
The present invention generally relates to parallel binary adders used in arithmetic logic units (ALUs) of microprocessors and, more particularly, to a low power, self-resetting adder with fast cycle time, minimum delay time and low latency. The parallel adder, due to its unique self-resetting design makes possible pipelined operations and good testability.
2. Background Description
Parallel binary adders are the basic building block of the arithmetic logic unit (ALU) of microprocessors, whether of the reduced instruction set computer (RISC) or complex instruction set computer (CISC) variety. The development of microprocessors is accelerating to provide greater numbers of transistors and higher numbers of millions of instructions per second (MIPS) performance, the emphasis being on improved performance and greater integration. The circuit density of modern microprocessors presents special problems, not the least of which is the increased power consumption and corresponding heat dissipation required with increased numbers of transistors on a chip. The high speed operation of the circuits comprising the microprocessors makes the circuits particularly susceptible to rate of change of current (di/dt) noise due to switching of large numbers of transistors on and off. Finally, the density of the circuits makes testing microprocessors for quality control purposes a difficult problem. There is therefore need for an improved high speed parallel adder which may be realized in integrated circuit (IC) densities required of modern microprocessors yet consumes minimum power, exhibits low noise and is readily testable.